## @file
#  ProjectMu QemuQ35Pkg
#
#  Package is a derivitive of the open source OVMF package.
#
#  Copyright (c) Microsoft Corporation
#
#  SPDX-License-Identifier: BSD-2-Clause-Patent
##

[Defines]
  DEC_SPECIFICATION              = 0x00010005
  PACKAGE_NAME                   = QemuQ35Pkg
  PACKAGE_GUID                   = 4544c001-2e3c-4ec0-b038-4fc68055beca
  PACKAGE_VERSION                = 0.1

[Includes]
  Include

[LibraryClasses]
  ##  @libraryclass  Verify blobs read from the VMM
  BlobVerifierLib|Include/Library/BlobVerifierLib.h

  ##  @libraryclass  Declares helper functions for Secure Encrypted
  #                  Virtualization (SEV) guests.
  MemEncryptSevLib|Include/Library/MemEncryptSevLib.h

  ##  @libraryclass  Provide common utility functions to PciHostBridgeLib
  #                  instances in ArmVirtPkg and OvmfPkg.
  PciHostBridgeUtilityLib|Include/Library/PciHostBridgeUtilityLib.h

  ##  @libraryclass  Parse the contents of named fw_cfg files as simple
  #                  (scalar) data types.
  QemuFwCfgSimpleParserLib|Include/Library/QemuFwCfgSimpleParserLib.h

[Guids]
  ## Policy GUID for GFX policy data
  #
  gPolicyDataGFXGuid =  { 0x3a1523c2, 0xbd10, 0x4a5d, { 0xa9, 0x86, 0x40, 0x5b, 0x85, 0x2f, 0xcb, 0xfc } }

  ## Token space GUID for QEMU Q35 package
  #
  gQemuQ35PkgTokenSpaceGuid = { 0xb7048716, 0x7d8b, 0x4a86, { 0x84, 0x95, 0x57, 0xa1, 0x76, 0x4f, 0x6e, 0xde } }

  gUefiQemuQ35PkgTokenSpaceGuid         = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}
  gOvmfPkKek1AppPrefixGuid              = {0x4e32566d, 0x8e9e, 0x4f52, {0x81, 0xd3, 0x5b, 0xb9, 0x71, 0x5f, 0x97, 0x27}}
  gOvmfPlatformConfigGuid               = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}
  gQemuRamfbGuid                        = {0x557423a1, 0x63ab, 0x406c, {0xbe, 0x7e, 0x91, 0xcd, 0xbc, 0x08, 0xc4, 0x57}}
  gXenBusRootDeviceGuid                 = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}
  gMicrosoftVendorGuid                  = {0x77fa9abd, 0x0359, 0x4d32, {0xbd, 0x60, 0x28, 0xf4, 0xe7, 0x8f, 0x78, 0x4b}}
  gEfiLegacyBiosGuid                    = {0x2E3044AC, 0x879F, 0x490F, {0x97, 0x60, 0xBB, 0xDF, 0xAF, 0x69, 0x5F, 0x50}}
  gEfiLegacyDevOrderVariableGuid        = {0xa56074db, 0x65fe, 0x45f7, {0xbd, 0x21, 0x2d, 0x2b, 0xdd, 0x8e, 0x96, 0x52}}
  gQemuKernelLoaderFsMediaGuid          = {0x1428f772, 0xb64a, 0x441e, {0xb8, 0xc3, 0x9e, 0xbd, 0xd7, 0xf8, 0x93, 0xc7}}
  gGrubFileGuid                         = {0xb5ae312c, 0xbc8a, 0x43b1, {0x9c, 0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}}
  gConfidentialComputingSecretGuid      = {0xadf956ad, 0xe98c, 0x484c, {0xae, 0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}}
  gConfidentialComputingSevSnpBlobGuid  = {0x067b1f5f, 0xcf26, 0x44c5, {0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}}

[Protocols]
  gXenBusProtocolGuid                   = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}
  gXenIoProtocolGuid                    = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}
  gIoMmuAbsentProtocolGuid              = {0xf8775d50, 0x8abd, 0x4adf, {0x92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}
  gEfiLegacy8259ProtocolGuid            = {0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1}}
  gEfiFirmwareVolumeProtocolGuid        = {0x389F751F, 0x1838, 0x4388, {0x83, 0x90, 0xcd, 0x81, 0x54, 0xbd, 0x27, 0xf8}}
  gEfiIsaAcpiProtocolGuid               = {0x64a892dc, 0x5561, 0x4536, {0x92, 0xc7, 0x79, 0x9b, 0xfc, 0x18, 0x33, 0x55}}
  gEfiIsaIoProtocolGuid                 = {0x7ee2bd44, 0x3da0, 0x11d4, {0x9a, 0x38, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
  gEfiLegacyBiosProtocolGuid            = {0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}}
  gEfiLegacyBiosPlatformProtocolGuid    = {0x783658a3, 0x4172, 0x4421, {0xa2, 0x99, 0xe0, 0x09, 0x07, 0x9c, 0x0c, 0xb4}}
  gEfiLegacyInterruptProtocolGuid       = {0x31ce593d, 0x108a, 0x485d, {0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}}
  gEfiVgaMiniPortProtocolGuid           = {0xc7735a2f, 0x88f5, 0x4882, {0xae, 0x63, 0xfa, 0xac, 0x8c, 0x8b, 0x86, 0xb3}}
  gOvmfLoadedX86LinuxKernelProtocolGuid = {0xa3edc05d, 0xb618, 0x4ff6, {0x95, 0x52, 0x76, 0xd7, 0x88, 0x63, 0x43, 0xc8}}

[PcdsFixedAtBuild]
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16

  ## This flag is used to control the destination port for PlatformDebugLibIoPort
  gUefiQemuQ35PkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4

  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0xc
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12
  gUefiQemuQ35PkgTokenSpaceGuid.PcdSecPeiTemporaryRamBase|0x0|UINT32|0x13
  gUefiQemuQ35PkgTokenSpaceGuid.PcdSecPeiTemporaryRamSize|0x0|UINT32|0x14
  gUefiQemuQ35PkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f

  ## Pcd8259LegacyModeMask defines the default mask value for platform. This
  #  value is determined.
  #  1) If platform only support pure UEFI, value should be set to 0xFFFF or
  #     0xFFFE; Because only clock interrupt is allowed in legacy mode in pure
  #     UEFI platform.
  #  2) If platform install CSM and use thunk module:
  #     a) If thunk call provided by CSM binary requires some legacy interrupt
  #        support, the corresponding bit should be opened as 0.
  #        For example, if keyboard interfaces provided CSM binary use legacy
  #        keyboard interrupt in 8259 bit 1, then the value should be set to
  #        0xFFFC.
  #     b) If all thunk call provied by CSM binary do not require legacy
  #        interrupt support, value should be set to 0xFFFF or 0xFFFE.
  #
  #  The default value of legacy mode mask could be changed by
  #  EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely need change it
  #  except some special cases such as when initializing the CSM binary, it
  #  should be set to 0xFFFF to mask all legacy interrupt. Please restore the
  #  original legacy mask value if changing is made for these special case.
  gUefiQemuQ35PkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x3

  ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy
  #  mode's interrrupt controller.
  #  For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.
  gUefiQemuQ35PkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x5

  gUefiQemuQ35PkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr|0x0|UINT32|0x17
  gUefiQemuQ35PkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize|0x0|UINT32|0x32

  ## Specify the extra page table needed to mark the GHCB as unencrypted.
  #  The value should be a multiple of 4KB for each.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|0x0|UINT32|0x3e
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize|0x0|UINT32|0x3f

  ## The base address of the SEC GHCB page used by SEV-ES.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecGhcbBase|0|UINT32|0x40
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecGhcbSize|0|UINT32|0x41
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase|0|UINT32|0x44
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize|0|UINT32|0x45

  ## The base address and size of the SEV Launch Secret Area provisioned
  #  after remote attestation.  If this is set in the .fdf, the platform
  #  is responsible for protecting the area from DXE phase overwrites.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdSevLaunchSecretBase|0x0|UINT32|0x42
  gUefiQemuQ35PkgTokenSpaceGuid.PcdSevLaunchSecretSize|0x0|UINT32|0x43

  ## The base address and size of a hash table confirming allowed
  #  parameters to be passed in via the Qemu firmware configuration
  #  device
  gUefiQemuQ35PkgTokenSpaceGuid.PcdQemuHashTableBase|0x0|UINT32|0x47
  gUefiQemuQ35PkgTokenSpaceGuid.PcdQemuHashTableSize|0x0|UINT32|0x48

  ## The base address and size of the work area used during the SEC
  # phase by the SEV and TDX supports.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfWorkAreaBase|0|UINT32|0x49
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfWorkAreaSize|0|UINT32|0x50

  ## The work area contains a fixed size header in the Include/WorkArea.h.
  # The size of this header is used early boot, and is provided through
  # a fixed PCD. It need to be kept in sync with any changes to the
  # header definition.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader|4|UINT32|0x51

  ## The base address and size of the TDX Cfv base and size.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdCfvBase|0|UINT32|0x52
  gUefiQemuQ35PkgTokenSpaceGuid.PcdCfvRawDataOffset|0|UINT32|0x53
  gUefiQemuQ35PkgTokenSpaceGuid.PcdCfvRawDataSize|0|UINT32|0x54

  ## The base address and size of the TDX Bfv base and size.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdBfvBase|0|UINT32|0x55
  gUefiQemuQ35PkgTokenSpaceGuid.PcdBfvRawDataOffset|0|UINT32|0x56
  gUefiQemuQ35PkgTokenSpaceGuid.PcdBfvRawDataSize|0|UINT32|0x57

  ## The base address and size of the SEV-SNP Secrets Area that contains
  #  the VM platform communication key used to send and recieve the
  #  messages to the PSP. If this is set in the .fdf, the platform
  #  is responsible to reserve this area from DXE phase overwrites.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSnpSecretsBase|0|UINT32|0x58
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSnpSecretsSize|0|UINT32|0x59

  ## The base address and size of a CPUID Area that contains the hypervisor
  #  provided CPUID results. In the case of SEV-SNP, the CPUID results are
  #  filtered by the SEV-SNP firmware. If this is set in the .fdf, the
  #  platform is responsible to reserve this area from DXE phase overwrites.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfCpuidBase|0|UINT32|0x60
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfCpuidSize|0|UINT32|0x61

  ## The range of memory that is validated by the SEC phase.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecValidatedStart|0|UINT32|0x62
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfSecValidatedEnd|0|UINT32|0x63

  ## The base address of the UART to use as the debugger port.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdDebuggerPortUartBase|0x3F8|UINT16|0x64

[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx]
  gUefiQemuQ35PkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10

[PcdsDynamic, PcdsDynamicEx]
  gUefiQemuQ35PkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21

  ## The IO port aperture shared by all PCI root bridges.
  #
  gUefiQemuQ35PkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22
  gUefiQemuQ35PkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23

  ## The 32-bit MMIO aperture shared by all PCI root bridges.
  #
  gUefiQemuQ35PkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24
  gUefiQemuQ35PkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25

  ## The 64-bit MMIO aperture shared by all PCI root bridges.
  #
  gUefiQemuQ35PkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26
  gUefiQemuQ35PkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27

  ## The following setting controls how many megabytes we configure as TSEG on
  #  Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defaults
  #  cause undefined behavior. During boot, the PCD is updated by PlatformPei
  #  to reflect the extended TSEG size, if one is advertized by QEMU.
  #
  #  This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).
  gUefiQemuQ35PkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20

  ## Set to TRUE by PlatformPei if the Q35 board supports the "SMRAM at default
  #  SMBASE" feature.
  #
  #  This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).
  gUefiQemuQ35PkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE|BOOLEAN|0x34

  ## This PCD adds a communication channel between OVMF's SmmCpuFeaturesLib
  #  instance in PiSmmCpuDxeSmm, and CpuHotplugSmm.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdCpuHotEjectDataAddress|0|UINT64|0x46

  ## This PCD specifies the event signaled by the EmuVariable library when FVB
  #  data is written.
  gUefiQemuQ35PkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2

[PcdsFeatureFlag]
  ## Informs modules (including pre-DXE-phase modules) whether the platform
  #  firmware contains a CSM (Compatibility Support Module).
  #
  gUefiQemuQ35PkgTokenSpaceGuid.PcdCsmEnable|FALSE|BOOLEAN|0x35

  ## Informs modules whether the platform firmware supports Standalone MM.
  #
  gUefiQemuQ35PkgTokenSpaceGuid.PcdStandaloneMmEnable|FALSE|BOOLEAN|0x100065
