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source/pip/qsharp/_adaptive_bytecode.py

132lines · modecode

1# Copyright (c) Microsoft Corporation.
2# Licensed under the MIT License.
3
4"""Shared opcode constants for the Adaptive Profile QIR bytecode interpreter.
5
6These constants define the bytecode encoding used by the Python AdaptiveProfilePass
7(emitter) and the Rust GPU receiver. Values must stay in sync with the Rust
8``bytecode.rs`` module and the WGSL interpreter.
9
10Opcode word layout::
11
12 bits [7:0] = primary opcode
13 bits [15:8] = sub-opcode / condition code
14 bits [23:16] = flags
15
16Compose via bitwise OR: ``opcode | (sub << 8) | flag``
17Example: ``OP_ICMP | (ICMP_SLE << 8) | FLAG_SRC1_IMM``
18"""
19
20# ── Flags (pre-shifted to bit 16+) ──────────────────────────────────────────
21FLAG_DST_IMM = 1 << 18 # dst field is an immediate value, not a register
22FLAG_SRC0_IMM = 1 << 16 # src0 field is an immediate value, not a register
23FLAG_SRC1_IMM = 1 << 17 # src1 field is an immediate value, not a register
24FLAG_AUX0_IMM = 1 << 19 # aux0 field is an immediate value, not a register
25FLAG_AUX1_IMM = 1 << 20 # aux1 field is an immediate value, not a register
26FLAG_AUX2_IMM = 1 << 21 # aux2 field is an immediate value, not a register
27FLAG_AUX3_IMM = 1 << 22 # aux3 field is an immediate value, not a register
28
29FLAG_FLOAT = 1 << 23 # operation uses float semantics
30
31
32# ── Control Flow ─────────────────────────────────────────────────────────────
33OP_NOP = 0x00
34OP_RET = 0x02
35OP_JUMP = 0x04
36OP_BRANCH = 0x05
37OP_SWITCH = 0x06
38OP_CALL = 0x07
39OP_CALL_RETURN = 0x08
40
41# ── Quantum ──────────────────────────────────────────────────────────────────
42OP_QUANTUM_GATE = 0x10
43OP_MEASURE = 0x11
44OP_RESET = 0x12
45OP_READ_RESULT = 0x13
46OP_RECORD_OUTPUT = 0x14
47
48# ── Integer Arithmetic ───────────────────────────────────────────────────────
49OP_ADD = 0x20
50OP_SUB = 0x21
51OP_MUL = 0x22
52OP_UDIV = 0x23
53OP_SDIV = 0x24
54OP_UREM = 0x25
55OP_SREM = 0x26
56
57# ── Bitwise / Shift ─────────────────────────────────────────────────────────
58OP_AND = 0x28
59OP_OR = 0x29
60OP_XOR = 0x2A
61OP_SHL = 0x2B
62OP_LSHR = 0x2C
63OP_ASHR = 0x2D
64
65# ── Comparison ───────────────────────────────────────────────────────────────
66OP_ICMP = 0x30
67OP_FCMP = 0x31
68
69# ── Float Arithmetic ─────────────────────────────────────────────────────────
70OP_FADD = 0x38
71OP_FSUB = 0x39
72OP_FMUL = 0x3A
73OP_FDIV = 0x3B
74
75# ── Type Conversion ──────────────────────────────────────────────────────────
76OP_ZEXT = 0x40
77OP_SEXT = 0x41
78OP_TRUNC = 0x42
79OP_FPEXT = 0x43
80OP_FPTRUNC = 0x44
81OP_INTTOPTR = 0x45
82OP_FPTOSI = 0x46
83OP_SITOFP = 0x47
84
85# ── SSA / Data Movement ─────────────────────────────────────────────────────
86OP_PHI = 0x50
87OP_SELECT = 0x51
88OP_MOV = 0x52
89OP_CONST = 0x53
90
91# ── ICmp condition codes (sub-opcode, placed in bits[15:8] via << 8) ─────────
92# Reference: https://llvm.org/docs/LangRef.html#icmp-instruction
93ICMP_EQ = 0
94ICMP_NE = 1
95ICMP_SLT = 2
96ICMP_SLE = 3
97ICMP_SGT = 4
98ICMP_SGE = 5
99ICMP_ULT = 6
100ICMP_ULE = 7
101ICMP_UGT = 8
102ICMP_UGE = 9
103
104# ── FCmp condition codes ─────────────────────────────────────────────────────
105# Reference: https://llvm.org/docs/LangRef.html#fcmp-instruction
106FCMP_FALSE = 0
107FCMP_OEQ = 1
108FCMP_OGT = 2
109FCMP_OGE = 3
110FCMP_OLT = 4
111FCMP_OLE = 5
112FCMP_ONE = 6
113FCMP_ORD = 7
114FCMP_UNO = 8
115FCMP_UEQ = 9
116FCMP_UGT = 10
117FCMP_UGE = 11
118FCMP_ULT = 12
119FCMP_ULE = 13
120FCMP_UNE = 14
121FCMP_TRUE = 15
122
123# ── Register type tags ───────────────────────────────────────────────────────
124REG_TYPE_BOOL = 0
125REG_TYPE_I32 = 1
126REG_TYPE_I64 = 2
127REG_TYPE_F32 = 3
128REG_TYPE_F64 = 4
129REG_TYPE_PTR = 5
130
131# ── Sentinel values ──────────────────────────────────────────────────────────
132VOID_RETURN = 0xFFFFFFFF # Function does not have a return value.
133